• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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    • 专利摘要:
    A low-voltage drop regulator comprising an error amplifier (AE) and a power stage (ETP) having an output terminal (BS) looped back to the error amplifier (AE) and adapted to output a output current in a load (RL, CL). The device comprises several main supply inputs (EALPi) intended to potentially receive respectively several different supply voltages, in that the power stage (ETP) comprises several conduction paths (PTHi) respectively connected between said main inputs power supply and said output terminal, individually selectable and each having an output transistor (MPgi), in that it further comprises a selection circuit (CSL) connected to said main power inputs and configured to select one conduction paths (PTHi) according to a selection criterion, and in that the error amplifier (AE) comprises an output stage (ETS) configured to selectively drive the output transistor (MPgi) of the path selected conduction.
    公开号:FR3051570A1
    申请号:FR1654576
    申请日:2016-05-23
    公开日:2017-11-24
    发明作者:Alexandre Pons
    申请人:STMicroelectronics Alps SAS；
    IPC主号:
    专利说明:

    Low voltage drop control device, in particular able to withstand supply voltages compatible with
    the standard USB type C
    Embodiments of the invention relate to low dropout voltage regulators ("LDO") and more particularly those compatible with the USB type C standard.
    The USB Type C standard is a new USB standard offering new features, including a reversible orientation of the USB connector and the direction of the USB cable. Moreover, the USB cable can withstand high powers, up to 60 watts for example, in charging applications, which implies high supply voltages, typically from 5 volts to 20 volts. However, other lower supply voltages are also possible, for example 2.7 volts to 5.5 volts.
    Type C controllers are used to manage USB cable detection (connection and type), communication protocol, and different power supply voltages.
    Identical C-type controllers can be located inside the source (the power supply, typically a battery charger that is plugged into the mains) but also inside the object that consumes the power (a mobile phone, a laptop, a tablet, ...) or inside the connectors USB cables for example.
    However, the supply voltages present in these different situations are generally of different values.
    According to one embodiment, it is therefore proposed an onboard low voltage drop regulator that can be powered by multiple power sources so as to generate a fixed supply voltage for the controller.
    According to one embodiment, it is proposed to produce such a regulator with a small footprint and using a power PMOS transistor only when the high supply voltage is selected and using conventional PMOS transistors for the other supply voltages.
    According to one aspect, a low-voltage drop regulator is proposed, comprising an error amplifier and a power stage having an output terminal looped back to the error amplifier and capable of delivering an output current. in a load.
    According to a general characteristic of this aspect, the control device comprises several main supply inputs intended to potentially receive respectively several different supply voltages. The power stage comprises several power path paths respectively connected between said main power inputs and said output terminal, individually selectable and each having an output transistor (or "gain" transistor).
    The term "many" is understood to mean "at least two".
    The regulating device further comprises a selection circuit connected to said main supply inputs and configured to select one of the conduction paths according to a selection criterion. The error amplifier also comprises an output stage (for example comprising a "small signal" gain stage) configured to selectively drive the output transistor of the selected conduction path.
    According to one embodiment, the error amplifier comprises an input stage having an input coupled to said output terminal, and the output stage comprises several modules respectively assigned to the conduction path, each module being coupled to the output of the input stage, at the main supply input connected to the corresponding conduction path, and configured to control or not the output transistor of the corresponding conduction path on command of the selection circuit.
    According to one embodiment, each module comprises a module input coupled to the output of the input stage of the error amplifier, a module output coupled to the gate of the corresponding output transistor, an input of a module power supply coupled to the corresponding main power input, and a gain stage connected between the module power input and the ground and having a module transistor connected between the module output and the ground and whose gate is connected to the module input and to the ground respectively via two switches respectively controllable by two complementary control signals delivered by the selection circuit.
    Each module advantageously comprises a Miller compensation circuit, connected between the drain and the gate of the module transistor.
    According to one embodiment, the selection circuit is powered by the output voltage present at said output terminal and the regulating device has a starting configuration in which each conduction path connected to a supply voltage actually present, is passing until said output voltage reaches a threshold value allowing the selection circuit to select one of the conduction paths.
    Furthermore, each module of the output stage of the error amplifier is advantageously configured for, in said startup configuration, to turn on the corresponding output transistor.
    Each output transistor is for example a PMOS transistor having its substrate connected to the corresponding main supply input and each module advantageously comprises a pull-down circuit connected between the module output and the ground. having a control input connected to said output terminal.
    This low excursion circuit comprises for example a first NMOS transistor connected between the module output and the ground, a resistor connected between the module supply input and the gate of the first transistor, a second NMOS transistor connected between the gate of the first transistor and the ground and whose gate is connected to said output terminal.
    According to one embodiment, each conduction path comprises a means that can be controlled by the selection circuit and configured to allow the selection or not of the conduction path and to make the conduction path go through during the start-up phase.
    This controllable means comprises for example a diode-mounted PMOS auxiliary transistor, connected between the output transistor and the output terminal, and controllable on its gate by means of a control transistor itself controllable on its gate by the selection circuit.
    This PMOS auxiliary transistor advantageously also has its substrate connected to the output terminal and its gate connected to the output terminal via a resistor.
    According to one embodiment, the selection circuit comprises a plurality of detection circuits respectively coupled to the main supply inputs and each configured to detect the crossing of a threshold by the corresponding supply voltage and to deliver a logic detection signal representative of the crossing or not of said threshold.
    The selection circuit further comprises a logic module configured to receive the detection logic signals and to deliver a selection signal representative of the selected conduction path according to said selection criterion.
    This selection criterion may advantageously correspond to the supply voltage present having the lowest value. The error amplifier could be powered with a separate supply voltage but it is particularly advantageous that it is powered by the supply voltage supplied to the output terminal of the regulating device.
    In other words, the input stage of the error amplifier has a power input advantageously connected to the output terminal. At least one of the output transistors is advantageously a specific "high voltage" compatible transistor, for example a power transistor, so as to be able to withstand a high supply voltage.
    In another aspect there is provided a controller, compatible with the standard USB type C, incorporating a low voltage drop control device as defined above.
    In another aspect there is provided an apparatus, for example a laptop, or a wireless communication device such as for example a cellular mobile phone or tablet, incorporating a controller as defined above.
    In another aspect, there is provided a DC power source charger, for example a battery charger, incorporating a controller as defined above.
    It is still proposed, in another aspect, a type C USB cable, incorporating a controller as defined above. Other advantages and features of the invention will appear on examining the detailed description of embodiments, which are in no way limiting, and the attached drawings in which: FIGS. 1 to 10 relate to various embodiments of the invention; invention.
    In FIGS. 1 to 3, the reference CTRL designates a USB controller compatible with the USB type C standard comprising one or several low voltage drop-off regulators 1 (LDO) intended to deliver a fixed regulated voltage to a front-end analog module (AFE). : Analogue Front end) 2 of classic structure and known per se, as well as a digital heart 3.
    In the embodiment of FIG. 1, the controller CTRL is placed in an APP device, for example a laptop or a wireless communication device such as a cellular mobile telephone, or a digital tablet.
    In this example, the controller can be powered by either a high voltage VBUS delivered by a USB cable type C referenced 5, for example having a level of 5 volts nominal but can vary from 5 volts to 20 volts typically, or by a voltage VBAT delivered by a DC power source 4, for example a battery, this voltage VBAT may for example vary between 2.8 volts and 4.8 volts.
    In the embodiment of FIG. 2, the controller CTRL is incorporated in a charger 7, for example a battery charger, having a plug 70 intended to be connected to the mains. The charger 7 is for example configured to supply the regulator 1 with a high voltage VBUS (from 5 volts to 20 volts) which can be conveyed on the USB cable 5, or else with an auxiliary voltage whose level can be for example 5 volts or 3.3 volts.
    In the embodiment of FIG. 3, the controller CTRL is disposed in the USB cable 5, and more particularly in each connector 50 and can then be powered by an auxiliary voltage coming from a first pin of the connector (for example the pin standardized under the name CCI) or by another auxiliary voltage coming from a second pin of the connector (for example the pin standardized under the name CC2), whose levels can vary from 2.7 volts to 5.5 volts for example.
    It can thus be seen that the low-voltage drop regulator 1 must be capable of delivering a fixed regulated voltage to the different elements of the CTRL controller regardless of the value of the regulator supply voltage that may come from several different power sources. .
    The regulator 1 incorporated in the controller CTRL is therefore a low voltage drop regulator that can be powered from multiple power sources to generate a fixed regulated voltage output.
    One embodiment will now be described more particularly, with reference to FIGS. 4 to 10, and an example of operation of such a regulator 1.
    Referring now more particularly to FIG. 4, it can be seen that the regulator 1, made for example in an integrated manner within an integrated circuit CI, comprises an error amplifier AE receiving a reference voltage VREF issued a reference voltage source, for example a band gap reference voltage source which is a voltage substantially independent of the temperature and which delivers a voltage around 1.25 volts, close to the band gap value of silicon at the temperature of 0 K which is equal to 1.22 electronvolts.
    The regulator 1 also comprises a power stage ETP having an output terminal BS looped back to the error amplifier via a PDV divider bridge (although this divider bridge is not absolutely essential) so as to deliver on the inverting input of the error amplifier a voltage equal to a.Vout where Vout is the output voltage delivered to the output terminal of the regulator and has the dividing ratio of the divider bridge PDV.
    The output voltage Vout is a regulated voltage, that is to say independent of the variations of the supply voltage which, in the present case, may be one of the voltages VBUS, VBAT, VAUX1 and VAUX2 likely to be available.
    For reasons of stability, the regulator 1 can be connected to a decoupling capacitor CL. Furthermore, in this FIG. 4, the reference RL represents the load of the regulator which can be, for example, the frontal analog module (AFE: Analogue Front end) 2 or the digital core 3 (FIGS. 1 to 3).
    In this embodiment, the regulator 1 consequently comprises four main supply inputs EALP1-EALP4 intended to potentially receive respectively several different supply voltages, in this case the voltages VBUS, VBAT, VAUX1 and VAUX2.
    As will be seen in more detail below, only one of these supply voltages may be present or several supply voltages may be present simultaneously.
    The voltage VBUS here is a high voltage which can typically vary from 5 volts to 20 volts while the voltage VBAT is a low voltage which can vary for example from 2.8 volts to 4.8 volts and that the voltages VAUX1 and VAUX2 are voltages averages ranging, for example, from 2.7 volts to 5.5 volts. The power stage ETP of the regulator 1 comprises several conduction paths, at least two and here four conduction paths, PTH1-PTH4 respectively connected between the main supply inputs EALP1-EALP4 and the output terminal BS.
    These conduction paths PTH1-PTH4 are individually selectable and each comprise an output transistor MPgi (i ranging from 1 to 4).
    The regulator 1 furthermore comprises a selection circuit CSL connected to the main supply inputs EALP1-EALP4 and configured to select one of the conduction paths PTH1-PTH4 according to a selection criterion of which an example will be given below. after.
    Finally, the error amplifier AE comprises in addition to the input stage ETE receiving the reference voltage VREF and the voltage a.Vout, an output stage ETS configured to selectively drive the output transistor MPgi of the selected conduction path iPTH.
    Reference will now be made more particularly to FIGS. 5 to 8 to describe in greater detail the various elements of this regulator 1.
    Referring now more particularly to FIG. 5, it can be seen that the input stage ETE of this regulator can be produced in a conventional manner by a differential pair biased by a current source I powered by the voltage Vout delivered. at the BS output terminal of the controller.
    The differential pair is connected to a current mirror.
    The differential pair comprises two PMOS transistors Ml and M2 connected by their source.
    The current mirror is formed by two transistors M3 and M4 connected by their gates, for example NMOS transistors. The sources of the transistors M3 and M4 are respectively connected to the drains of the transistors M1 and M2 of the differential pair.
    The gate of the transistor Ml corresponds to the positive input of the error amplifier AE and therefore receives the reference voltage VREF.
    The gate of the transistor M2 corresponds to the inverting input of the amplifier and receives the voltage a.Vout.
    The drain of the transistor M2 forms the output of this input stage ETE and provides a voltage VDIFF. The ETS output stage comprises several modules, here four modules MD1-MD4 (FIG. 4) respectively assigned to the conduction paths PTH1-PTH4.
    Each module MDi is coupled to the output of the input stage of the error amplifier AE and is also coupled to the main supply input EALPi connected to the corresponding conduction path PTHi.
    Each module is configured to control or not the output transistor MPgi of the corresponding conduction path PTHi of the selection circuit CSL.
    Referring now more particularly to Figure 6 to describe in more detail an embodiment of a module MDi. The architecture of all MDi modules is identical. Only the values of certain components change to adapt in particular to the characteristics of the corresponding output transistor.
    Each module MDi comprises a module input EMDi coupled to the output of the input stage ETE of the error amplifier AE to receive the voltage VDIFF.
    The module MDi also comprises a SMDi module output coupled to the gate of the corresponding output transistor MPgi. The SMDi module output delivers the Vgate_i signal.
    The module MDi comprises a module supply input EALMi coupled to the corresponding main supply input EALPi.
    The module MDi also comprises a gain stage in common source assembly ETGi, connected between the module supply input EALMi and GND ground.
    This gain stage (small signal) comprises a module transistor Mfi, here an NMOS transistor, connected between the module output SMDi and the ground GND. The gate of this module transistor Mfi is connected to the module input EMDi via a first switch Ili controlled by a control signal SWi.
    The gate of the module transistor Mfi is also connected to the ground GND via a second switch I2i controlled by a control signal / SWi, complementary to the control signal SWi. The gain stage further comprises a resistor Zi, the value of which forms the value of the output impedance of the gain stage, connected between the module output SMDi and the module supply input EALMi.
    As will be seen in more detail below, the selection circuit CSL is supplied by the output voltage present at the output terminal and the regulating device 1 has a start configuration in which each conduction path PTHi connected to a supply voltage actually present, is passed until the output voltage Vout reaches a threshold value allowing the selection circuit CSL to enter into operation and select one of the conduction paths according to the selection criterion . In this respect, each module MDi is configured for, in this startup configuration, to turn on the corresponding output transistor MPgi. For this purpose, each output transistor MPgi being a PMOS transistor, each module comprises a pull-down circuit (pull-down circuit) CPDi connected between the module output SMDi and the ground GND.
    More precisely, this pull-down circuit CPDi comprises a first NMOS transistor Ms1 connected between the module output SMDi and the ground GND, a resistor Rs connected between the module supply input EALMi and the gate of the first transistor Ms1. a second transistor Ms2 connected between the gate of the first transistor Ms1 and the ground, and whose gate, forming a control input for this pull-down circuit, is connected to the output terminal BS to receive, via the PDV divider bridge , the tension aVout.
    As will be seen in more detail below, during the start-up phase, this circuit CPDi ensures that the signal Vgate i is pulled to ground in the presence of the corresponding supply voltage, as long as the selection circuit is not connected. not operational, so as to turn the output PMOS transistor MPgi during this startup phase.
    Finally, although this is not essential, the module MDi comprises a Miller compensation circuit, of conventional structure, connected between the drain and the gate of the module transistor Mfi.
    This Miller CCMi compensation circuit comprises a capacitor CMi connected in series with a resistor RMi.
    The Miller compensation circuit makes it possible to improve the stability of the feedback loop connecting the output terminal BS to the inverting input of the first stage ETE of the error amplifier AE.
    The values of the capacitor CMi and of the resistor RMi are determined in a conventional manner as a function of the characteristics of the corresponding output transistor MPgi, the characteristics of the input stage of the error amplifier and the range of variations of the output load.
    Referring now to FIG. 4, the architecture of the power stage ETP is described in more detail.
    The latter comprises as many PTHi conduction paths as potential power sources and therefore AELPi main power inputs.
    This power stage ETP is configured to allow direct management of these multiple conduction paths so as to select one at the end of the start phase, without using a conventional structure that would use a single path of conduction in combination with several conventional switches to select the desired supply voltage. Since the architecture of each conduction path is identical, only one of these conduction paths will be described here, for example the PTHI conduction path.
    The conduction path PTHI comprises the output transistor or gain transistor MPgl which is here a PMOS transistor working in its saturation region with the substrate connected to the main supply input EALP1.
    The PTHI conduction path also comprises a PMOS auxiliary transistor MPpl, or protective transistor, mounted in a diode (its gate is connected to its drain via a resistor RI). The reference DSI designates the intrinsic substrate diode for this transistor which participates in the operation of the diode transistor during the start-up phase. This diode DSI is conducting because of the connection of the transistor MPpl substrate to the output terminal BS and, in the case of a PMOS transistor, it is constituted by the P-doped drain zone and the N-doped substrate zone.
    This auxiliary transistor MPpl is connected between the output transistor MPgl and the output terminal BS and, when the conduction path is selected, it operates in its linear region with its substrate connected to the output terminal BS. In the start-up phase, it operates as a diode as previously indicated.
    This auxiliary transistor MPpl is controllable on its gate via resistor R1 (which allows diode mounting of the transistor) and a control transistor TCM1 which is itself controllable on its gate by a control signal SEL1. delivered by the selection circuit CSL.
    In the example described here, among the four conduction paths PTH1-PTH4, a path, namely the path PTH1, is a high voltage path dedicated to the supply VBUS, another path, namely the path PTH2, is a low voltage path dedicated to the VBAT power supply delivered by a battery, and the other two paths namely the PTH3 and PTH4 paths are medium voltage paths dedicated to auxiliary power supplies VAUX1 and VAUX2.
    As a result, the only specific high voltage component is the output transistor MPgl which is, for example, a PMOS power transistor of the extended drain type. All other PMOS transistors are conventional transistors achievable in CMOS technology.
    In a conventional controller architecture using a single conduction path in combination for example with four controllable switches for selecting a supply voltage from among four possible supply voltages, it would be necessary to have five power transistors, namely four power transistors for the four switches dedicated to the four possible supply voltages (whether the power supply is a high voltage supply or not) and a power transistor for the conduction path. The invention thus makes it possible to save four power transistors here, which makes it possible to advantageously reduce the surface area of the regulator.
    Reference is now made more particularly to FIG. 7 to describe the structure of the selection circuit CSL.
    The selection circuit CSL comprises a plurality of detection circuits CDT1-CDT4 respectively coupled to the main supply circuit EALP1-EALP4.
    Each detection circuit CDTi is configured to detect the crossing of a threshold by the corresponding supply voltage possibly present at the main supply input EALPi and to deliver a logic detection signal VINi OK representative of the crossing or not of this threshold. .
    Each detection circuit comprises a comparator CMPi whose non-inverting input is connected to the corresponding main supply input via a voltage divider bridge and whose inverting input receives a reference voltage VREF2 resulting from a reference voltage source REF2.
    This reference voltage VREF2 may be identical to or different from the voltage VREF received on the non-inverting input of the input stage ETE of the error amplifier AE.
    The different comparators CMP1-CMP4 are powered by the voltage V available at the output terminal BS of the controller.
    In addition to the detection circuits CDTi, the selection circuit comprises a logic module MDL, also powered by the voltage Vout, receiving all the logic detection signals VINi OK and configured to deliver on the one hand the control signals SELi to the control transistors. TCMi (FIG. 4) and secondly the control signals SWi to the module MDi of the output stage ETS.
    The control signals SELi and SWi together form selection signals making it possible to select one of the conduction paths and to "open" the other paths.
    Each logic signal VINi OK takes the value 1 when the supply voltage becomes greater than VREF2 / b, where b is the division ratio of the associated divider bridge.
    Otherwise, the logical signal VINi_OK keeps the value 0.
    The logic module MDL comprises a set of logic gates whose structure is defined from the desired selection criterion, knowing that a single control signal SELi must be active (equal to 1) at a time.
    The selection criterion can be the following.
    If only one supply voltage is present, this voltage must be selected.
    If several supply voltages are present, one will choose the one having the lowest value, which makes it possible to minimize the power consumed.
    An example of a selection scheme is illustrated in FIG. 8, a diagram for which it is considered that the regulator 1 comprises three main supply inputs EALP1-EALP3 intended respectively to potentially receive the high supply voltage VBUS, the low voltage of VBAT power supply and an average supply voltage VAUX.
    In the starting phase, no supply voltage is still present, and the three logic signals VINIOK, VIN2 0K and VIN3 0K are at 0 as well as the three control signals SEL1-SEL3. As soon as the voltage VAUX has crossed its threshold (VIN3_OK = 1) then the logic module MDL is configured to confer the logic value 1 to the control signal SEL3 and the logic value 0 to the control signals SEL1 and SEL2, if the logic signal VIN2_OK is null and this whatever the logical value of the signal VIN1_OK.
    In other words, the voltage VAUX will then be selected, whether this voltage is the only one present or that it is present simultaneously with the voltage VBUS, since the voltage having the lowest value is selected.
    Similarly, as soon as the detection logic signal VIN2 0K takes the logic value 1, then the logic module MDL is configured to confer the logic value 1 to the control signal SEL2 and the logic value 0 to the control signals SEL1 and SEL3, and whatever the logical value of the signals VIN1_OK and VIN3 0K.
    In other words, it is this time the voltage VBAT will be selected, whether alone or in the presence of the other two supply voltages since it is the lowest voltage.
    Finally, in the presence of logic signals VIN2 0K and VIN3 0K equal to 0, the control signal SEL1 will take the value 1 as soon as the detection logic signal VINI OK takes the value 1, which corresponds to the selection of the voltage of VBUS power supply which is then considered to be the only power supply available.
    Moreover, as long as a control signal SELi is at 0, the signal SWi is at 0 now open the switch Ili (FIG. 6) while the signal / SWi is at 1, closing the switch I2i to connect the gate from transistor Mfi to ground.
    We will now describe a mode of operation of the regulator according to the invention.
    In the start-up phase, all the conduction paths are active, that is to say that a conduction path is capable of being switched on as soon as the corresponding supply voltage actually present at the input of this input is rising. conduction path.
    Indeed, if we consider the conduction path PTHi, as soon as the value of the supply voltage associated with this conduction path, initially at 0, increases, the pull-down circuit CPDi of the module MDi (FIG. 6) pulls the gate of the output transistor MPgi corresponding to ground (Vgate i is pulled to 0).
    Indeed, the voltage aVout present on the gate of the transistor Ms2 is not sufficient to make this transistor passing. This transistor is thus blocked and the resistor Rs is chosen so that the voltage present at the gate of the transistor Ms1 is greater than the threshold voltage of this transistor to make it on, thereby connecting the gate of the output transistor MPgi to the mass.
    The transistor MPgi is therefore passing.
    Moreover, although the auxiliary transistor MPpi is blocked since the corresponding control signal SELi is at 0, the current can flow through this transistor since it is diode-mounted.
    Thus, as soon as a supply voltage rises, it begins to charge the output capacitor CL through the corresponding output transistor MPgi and through the diode of the auxiliary transistor MPpi.
    The output voltage Vout then follows the difference between the value of this supply voltage decreased by the threshold voltage of the diode. And, there is no risk of reverse current due to the diode-mounted auxiliary transistor and substrate diodes DSi of these auxiliary transistors arranged upside down. As soon as the output voltage Vout reaches a threshold value, for example a threshold value equal to the value of a "power-on reset" system (for example between 1.2 and 1.5 volts), the selection circuit CSL powered by this voltage Vout can work and determine which path to select. In this respect, the control signal SELi corresponding to the selected path takes the value 1, which turns on the control transistor TCMi (FIG. 4), which consequently draws the gate of the auxiliary transistor MPpi to ground so as to to make totally passing.
    Moreover, the transistor Ms2 of the module MDi becomes on, which blocks the transistor Msl. On the other hand, the signal SWi takes the value 1, which closes the switch Ili and opens the switch I2i, turning on the module transistor Mfi. The regulation loop is then active via the error amplifier AE. The gate of transistor MPgi is pulled to a potential guaranteeing the regulation of the output voltage at the target voltage. It should be noted that this mechanism works even if multiple supply voltages start at the same time. Thus, as explained above, as long as the output voltage Vout does not reach its threshold, the selection circuit is inoperative but the paths corresponding to the supply voltages actually present which rise at the same time, are on and voltage output Vout follows the highest supply voltage minus the threshold voltage of the diode. As soon as the output voltage Vout becomes greater than the threshold, the selection circuit operates and passes the selected conduction path while opening the other conduction paths.
    And, as the controller operates continuously, if at any given time the configuration of the supply voltages present at the main inputs is changed, the selection circuit can select another supply voltage associated with another conduction path.
    These operating mechanisms are illustrated on two examples (FIG. 9 and FIG. 10).
    In FIG. 9, it is assumed that only the high voltage VBUS is present.
    In FIG. 9, the curve C1 illustrates the temporal evolution of the voltage VBUS while the curve C2 illustrates the temporal evolution of the output voltage Vont. At time t0, the voltage VBUS begins to rise. Given the transistor mounted diode in the corresponding conduction path, the voltage Vont starts to rise at time tl to follow the voltage VBUS at the diode threshold voltage near.
    Then, at time t2, the output voltage Vont has reached its threshold allowing the selection circuit to operate. This then selects the conduction path associated with the voltage VBUS which allows the voltage Vout to join the voltage VBUS at time t3. Between the instant t3 and t4 the voltage Vout reaches the setpoint voltage imposed by the reference voltage VREF (that is to say the setpoint voltage equal to VREF / a) and beyond the instant t4, we have the regulation phase.
    In FIG. 10, it is assumed that the voltages VBUS and VBAT are available simultaneously.
    In this FIG. 10, the curve C1 illustrates the temporal evolution of the voltage VBUS, the curve C2 illustrates the temporal evolution of the voltage VBAT and the curve C3 illustrates the temporal evolution of the voltage Vout. At time t0, the two voltages VBUS and VBAT start to rise.
    Due to the corresponding transistors mounted in diodes, the voltage Vout follows the highest supply voltage, in this case the VBUS voltage, to the diode threshold value.
    Then, at time t2, the selection circuit comes into operation and it selects the conduction path associated with the voltage VBAT which is the lowest voltage.
    Voltage V then reaches at time t3 the voltage VBAT and between times t3 and t4 follows this voltage VBAT to reach the setpoint. The linear regulation phase continues beyond time t4.
    In order to obtain a good performance of the regulator (in terms of PSSR: "Power Supply Rejection Ratio") under conditions of low voltage drop, it is recommended to keep the output transistor MPgi corresponding in its saturation region even in the minimum feeding conditions.
    The operating conditions of the transistor being as follows:
    Vt <Vgs <Vds + Vt, this leads to a surface of the transistor MPgi proportional to the inverse of the square root of the voltage drop. Also, a large voltage drop on the high voltage transistor has a major impact on the reduction of the surface.
    This gives a reduction in the surface area of the regulator in a ratio 2 to 3 compared to a conventional architecture with a single conduction path. The invention is not limited to the embodiments which have just been described but encompasses all the variants.
    Thus, it would be possible to use instead of the "pull down" circuit in the MDi module, a comparator circuit which would receive on its non-inverting input the supply voltage and a reference voltage on its inverting input. Furthermore, other architectures are possible for the ETS output stage such as, for example, push-pull assemblies or the use of buffer stages.
    However, the architecture described above has the advantage that when the power supplies are present at startup, the selection circuit is off. And when the power supplies are sufficient to power the selection circuit (sufficient output voltage), the selection circuit couples the unused power supplies (defined by the selection criterion) and retains only the power supply for supplying the USB controller.
    This avoids unknown states with open switches, allowing predictive and healthy starts.
    Moreover, the selection circuit is powered by the output of the regulator, it does not have to handle high voltage, which simplifies its implementation (use of conventional transistors).
    权利要求:
    Claims (18)
    [1" id="c-fr-0001]
    A low voltage drop control device comprising an error amplifier (AE) and a power stage (ETP) having an output terminal (BS) looped back to the error amplifier (AE) and adapted to supplying an output current in a load (RL, CL), characterized in that it comprises several main supply inputs (EALPi) intended to potentially receive respectively several different supply voltages, in that the power stage (ETP) comprises a plurality of conduction paths (PTHi) respectively connected between said main supply inputs and said output terminal, individually selectable and each comprising an output transistor (MPgi), in that it further comprises a circuit for selection (CSL) connected to said main power inputs and configured to select one of the conduction paths (PTHi) according to a selection criterion, and the error amplifier (AE) comprises an output stage (ETS) configured to selectively drive the output transistor (MPgi) of the selected conduction path.
    [2" id="c-fr-0002]
    The device according to claim 1, wherein the error amplifier (AE) comprises an input stage (ETE) having an input (-) coupled to said output terminal (BS) and the output stage ( ETS) comprises a plurality of modules (MDi) respectively allocated to the conduction paths, each module (MDi) being coupled to the output of the input stage, to the main supply input (EALPi) connected to the corresponding conduction path , and configured to control or not the output transistor (MPgi) of the corresponding conduction path on command of the selection circuit (CSL).
    [3" id="c-fr-0003]
    3. Device according to claim 2, wherein each module (MDi) comprises a module input (EMDi) coupled to the output of the input stage (ETE) of the error amplifier. a module output (SMDi) coupled to the gate of the corresponding output transistor, a module supply input (EALMi) coupled to the corresponding main power input (EALPi), and a gain stage (ETGi) connected between the module supply input and the ground and having a module transistor (Mfi) connected between the module output and the ground and whose gate is connected to the module input and to the ground via respectively two switches (Ili, I2i) respectively controllable by two complementary control signals issued by the selection circuit (CSL).
    [4" id="c-fr-0004]
    4. Device according to claim 3, wherein each module (MDi) comprises a Miller compensation circuit (CCMi) connected between the drain and the gate of the module transistor.
    [5" id="c-fr-0005]
    5. Device according to one of the preceding claims, wherein the selection circuit is powered by the output voltage present at said output terminal, and the device has a startup configuration in which each conduction path connected to a voltage d supply actually present, is passing until said output voltage reaches a threshold value allowing the selection circuit (CSL) to select one of the conduction paths.
    [6" id="c-fr-0006]
    6. Device according to claims 2 and 5, wherein each module (MDi) is configured for, in said startup configuration, turn on the corresponding output transistor (MPgi).
    [7" id="c-fr-0007]
    The device of claim 6, wherein each output transistor (MPgi) is a PMOS transistor having its substrate connected to the corresponding main power input (EALPi) and each module (MDi) comprises a pull-down circuit. (CPDi) connected between the module output and ground and having a control input connected to said output terminal.
    [8" id="c-fr-0008]
    8. Device according to claim 7, wherein the pull-down circuit (CPDi) comprises a first NMOS transistor (Msl) connected between the module output and the ground, a resistor (Rs) connected between the power input module and the gate of the first transistor (Ms1), a second NMOS transistor (Ms2) connected between the gate of the first transistor (Ms1) and the ground and whose gate is connected to said output terminal.
    [9" id="c-fr-0009]
    9. Device according to one of the preceding claims taken in combination with claim 5, wherein each conduction path (PTHi) comprises a means (MPpi) controllable by the selection circuit, configured to allow the selection or not the path of conduction and to turn on the conduction path during the start-up phase.
    [10" id="c-fr-0010]
    The device according to claim 9, wherein said controllable means (MPpi) comprises a PMOS auxiliary transistor (MPpi) having its substrate connected to the output terminal (BS) and its gate connected to the output terminal (BS) by the intermediate of a resistor (Ri), the auxiliary transistor being connected between the output transistor (MPgi) and the output terminal (BS), and controllable on its gate via a control transistor (TCMi) commandable on its gate by the selection circuit (CSL).
    [11" id="c-fr-0011]
    11. Device according to one of the preceding claims, wherein the selection circuit comprises a plurality of detection circuits (CDTi) respectively coupled to the main supply inputs (EALPi) and each configured to detect the crossing of a threshold by the voltage corresponding power supply and deliver a logic detection signal (VINi_OK) representative of the crossing or not of said threshold, and a logic module (MDL) configured to receive the logic detection signals and to deliver a selection signal (SELi, SWi) representative the conduction path selected according to said selection criterion.
    [12" id="c-fr-0012]
    12. Device according to one of the preceding claims, wherein the selection criterion corresponds to the present supply voltage having the lowest value.
    [13" id="c-fr-0013]
    Device according to one of the preceding claims, wherein the error amplifier (AE) comprises an input stage (ETE) having an input (-) coupled to said output terminal and a connected power input. at the output terminal (BS).
    [14" id="c-fr-0014]
    14. Device according to one of the preceding claims, wherein at least one of the output transistors is a power transistor (MPgl).
    [15" id="c-fr-0015]
    15. Controller, compatible with the USB type C standard, incorporating a low-voltage regulation device (1) according to one of claims 1 to 14.
    [16" id="c-fr-0016]
    Controller incorporating apparatus (CTRL) according to claim 15.
    [17" id="c-fr-0017]
    A continuous power source charger incorporating a controller (CTRL) according to claim 15.
    [18" id="c-fr-0018]
    18. Type C USB cable incorporating a controller (CTRL) according to claim 15.
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    同族专利:
    公开号 | 公开日
    EP3249491A1|2017-11-29|
    US10303192B2|2019-05-28|
    EP3249491B1|2020-10-14|
    CN107422776A|2017-12-01|
    US10423179B2|2019-09-24|
    US20190235551A1|2019-08-01|
    CN107422776B|2019-07-09|
    US20170336819A1|2017-11-23|
    FR3051570B1|2019-11-22|
    CN206460351U|2017-09-01|
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    法律状态:
    2017-04-20| PLFP| Fee payment|Year of fee payment: 2 |
    2017-11-24| PLSC| Publication of the preliminary search report|Effective date: 20171124 |
    2018-04-23| PLFP| Fee payment|Year of fee payment: 3 |
    2019-04-19| PLFP| Fee payment|Year of fee payment: 4 |
    2020-04-22| PLFP| Fee payment|Year of fee payment: 5 |
    2022-02-11| ST| Notification of lapse|Effective date: 20220105 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1654576A|FR3051570B1|2016-05-23|2016-05-23|CONTROL DEVICE WITH LOW VOLTAGE DROP, ESPECIALLY CAPABLE OF SUPPORTING POWER SUPPLY VOLTAGES COMPATIBLE WITH TYPE C USB STANDARD|
    FR1654576|2016-05-23|FR1654576A| FR3051570B1|2016-05-23|2016-05-23|CONTROL DEVICE WITH LOW VOLTAGE DROP, ESPECIALLY CAPABLE OF SUPPORTING POWER SUPPLY VOLTAGES COMPATIBLE WITH TYPE C USB STANDARD|
    EP16201128.2A| EP3249491B1|2016-05-23|2016-11-29|Low drop out regulator, in particular capable to be supplied with supply voltages compatible with type c usb standard|
    US15/364,392| US10303192B2|2016-05-23|2016-11-30|Low drop out regulator compatible with type C USB standard|
    CN201611194036.3A| CN107422776B|2016-05-23|2016-12-21|Low difference voltage regulator|
    CN201621410466.XU| CN206460351U|2016-05-23|2016-12-21|The controller of low difference voltage regulator unit, electronic equipment and compatibility USB c-type standards|
    US16/381,541| US10423179B2|2016-05-23|2019-04-11|Low drop out regulator compatible with type C USB standard|
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